| Name | Version | Summary | date |
| tsfpga |
13.1.1 |
A flexible and scalable development platform for modern FPGA projects |
2025-02-12 13:43:08 |
| hdl-registers |
7.0.3 |
An open-source HDL register interface code generator fast enough to run in real time |
2025-02-11 11:06:19 |
| pyhdl-if |
0.0.1.13254700022 |
Python interface for HDL programming interfaces |
2025-02-11 02:36:59 |
| hdltree |
0.3.4 |
Pure Python HDL parser, plus symbol generator and sphinx domain |
2025-02-06 01:22:43 |
| vsg |
3.28.0 |
VHDL Style Guide |
2024-12-07 20:58:15 |
| mooreio-client |
2.0.4 |
CLI tool to automate EDA tasks for ASICs, FPGAs, and UVM IP. |
2024-11-28 20:18:13 |
| wal-lang |
0.8.2 |
Wal - Wavefile Analysis Language |
2024-10-09 11:00:08 |
| mio-cli |
1.3.8 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2024-05-17 12:13:59 |
| pyhdl-call-if |
0.0.1.8682446142 |
Python interface for HDL programming interfaces |
2024-04-15 02:48:41 |
| pyhdl-tlm-if |
0.0.1 |
Python interface for HDL programming interfaces |
2024-04-13 19:18:52 |
| pyhdl-pi-if |
0.0.1.8675558542 |
Python interface for HDL programming interfaces |
2024-04-13 18:44:50 |